1. Field of the Invention:
The present invention relates to a device and a method for reading out a predetermined data word from a memory and to a device and a method for storing a data block in a memory, in particular a memory where one-bit errors may sporadically occur, such as, for example, flash memories.
2. Description of the Related Art:
Many of today's memory technologies have the problem that individual bit errors may sporadically occur. This is unavoidable. However, the problem is generally limited to individual widely scattered bits. Multi-bit errors in a limited data region do occur, however they occur so sparsely that they generally do not pose a reliability problem. However, the reliability of many memory products suffers from the individual errors or one-bit errors. For this reason, data stored in memory elements are provided with redundancy information allowing these errors to be recognized and, if applicable, even corrected. A plurality of memory technologies are affected by this, among which, exemplarily, are special flash memory technologies and other non-volatile memory (NVM) types, but also different memory types.
Especially in the field of non-volatile memory types, in particular in flash memory products and flash memory technologies, individual bit errors may occur due to the internal connection of these memories, exemplarily due to a mechanism known as “drain disturb”, in repeated writing memory accesses. Apart from flash memories, this problem also occurs in other memory types. RAM (random access memory) memories used, for example, as operating memories are an example of this. There are sporadic one-bit errors in the field of RAM memories due to a particles which may, for example, originate from the potting mass of such a memory element.
Up to now, this problem has been solved by adding an error code per memory block, the memory being organized into individual memory blocks and every memory block including one or several data words. Both error detecting codes (EDCs and error correcting codes (ECCS) are employed here as error codes. For checking the correctness of a datum stored in a memory block, in this case, however, at first the entire memory block has to be read out to be able to check the datum or code for errors using the error code associated with the memory block. However, this procedure has some disadvantages.
If a very small memory block is chosen as a basic unit, the code expenditure, i.e. in particular the memory space, required for storing the error correction value, is very large compared to the size of a memory block. As is exemplarily explained in the book “Halbleiterschaltungstechnik” by U. Tietze and Ch. Schenk (Springer-Verlag, Berlin 1990, 9th Edition), the minimum number of bits of an error correction value allowing any one-bit error to be corrected is 3 bits for a datum having a length between one and 4 bits, is 4 bits for a datum having a length between 5 and 11 bits, is 5 bit for a datum having a length between 12 and 26 bits, is 6 bits for a datum having a length between 27 and 57 bits, is 7 bits for a datum having a length between 58 and 120 bits and is 8 bits for a datum having a length between 121 and 247 bits. These numbers make it clear that the memory expenditure for storing an error correction value as an error code for small memory block entails relatively high memory expenditure, i.e. in relation to the memory length required for storing the error code referenced to the size of the underlying datum. However, on the other hand a small memory unit can be accessed quickly and in an energy-efficient manner.
If, however, a greater block unit or size of the underlying memory block is chosen, the additional expenditure for the error code or the error correction value will be tolerable, however, the access will become very slow and energy-intensive or current-devouring due to the requirement of reading the entire block, even if only an individual byte is required.
If, for example, a data block has a net data block size of 16 bytes or 128 bits comprising sub-words or data words each including 4 bytes, the entire 16 bytes will have to be read for accessing an individual byte to be able to check the individual byte for an error. This produces a time lag of at least 3 or 4 clocks for reading the 3 data words not including this individual byte.
A way of compensating the slow access problem in the case of a greater memory block is installing and using a cache memory. However, cache memories cannot always compensate this disadvantage, which is particularly true in the case of a poor hit rate. In the case of a poor hit rate, required data frequently not cached or stored in the cache memory are requested by a processor or another component of the overall system including the memory. In this case, using a cache memory cannot accelerate the data access since in this case the entire memory block of the memory still has to be read for providing the datum desired in order to rule out an error.